We can combine it with PMU to observe the system forward guarantee situation. e.g., If too many "1" failure codes exist, the cache contention is serious. If too many "2" failure codes exist, there may be too many exceptions or interruptions. We will even introduce more failure codes in the future. e.g., "3" represents the reason for inter SMT harts contention.
In the current ISA spec, separating LR/SC from AMO is non-suitable; That would trap vendors from implementing balanced atomic primitives (Power is balanced. If a vendor wants weak, AMO also needs weak). We could describe it from the reason of SC and leave more freedom to micro-arch. Currently, I hope it would help define forward progress guarantee levels with litmus.
