IOMMU: We await an updated draft and hope to provide final review very soon.

Zc*: Recently proposed names for the new instruction formats have been approved with light modification.

WFMI: The question was raised whether this proposed new instruction opens a virtualization hole; analysis is forthcoming.

Ssecorrupt: the proposed RAS exception cause code will be incorporated into priv-1.13, and the proposed local interrupt codes will be incorporated into the AIA spec.

Vector crypto: We await the TG's research on the appropriateness of the semantics of the vghmac instruction.  Additionally, we offered further guidance on the definition of the vandn.vi instruction.

We approved the request to pursue a Supervisor Counter Delegation proposal as a fast-track extension.

We discussed whether it is legal for accesses to the time CSR to raise a visible trap when executed in M-mode.  We concluded that this is valid, so long as the implementation does not claim to support the Zicntr extension in M-mode.  The implementation might still claim to support the Zicntr extension in a less-privileged mode, as long as the instruction appears to execute correctly in that mode (e.g., if it is emulated via an invisible trap).