Just writing to confirm that there is no information regards to the # of PMP entries supported by hart mentioned in privilege spec . If my understanding is correct, then this information is good to go to RISC-V configurations structure.

 

-          Abner

 

From: tech-privileged@... [mailto:tech-privileged@...] On Behalf Of Andrew Waterman
Sent: Saturday, May 23, 2020 6:31 AM
To: Tariq Kurd <tariq.kurd@...>
Cc: tech-privileged@...
Subject: Re: [RISC-V] [tech-privileged] Extending the number of PMP entries

 

I've made a pull request to extend the number of PMP entries, and have attached the compiled PDF for convenience.  Feedback and error detection are appreciated: the fact that there used to be 16 PMP entries manifested in several places in the document.

 

https://github.com/riscv/riscv-isa-manual/pull/525

 

On Fri, May 22, 2020 at 12:30 AM Tariq Kurd <tariq.kurd@...> wrote:

Hi Andrew,

 

That’s fine for me. Implementing 0 / 16 / 64 PMP entries is ok

 

Tariq

 

From: Andrew Waterman [mailto:andrew@...]
Sent: 21 May 2020 17:50
To: Tariq Kurd <tariq.kurd@...>
Cc: tech-privileged@...
Subject: Re: [RISC-V] [tech-privileged] Extending the number of PMP entries

 

 

 

On Thu, May 21, 2020 at 8:17 AM Mr Tariq Kurd <tariq.kurd@...> wrote:

Hi everyone,

 

Can we allocate more CSRs so that we can have more PMP entries available? We already have one implementation which requires 20 PMP entries, for example.

Currently the CSR address space can allow up to 64 PMP entries (unless CSRs have been allocated which I don’t know about).

0x3A4 – 0x3AF could become pmpcfg4-15

0x3C0 – 0x3EF could become pmpaddr16-63

 

64 entries would be more than enough (I don’t envisage needing more than 32), but I don’t know about other users.

 

I’m happy to allocate the PMP entries in blocks of 16, for example, and make higher numbered unused entries read-only-zero to save area.

So in our case we would implement the CSRs for 32 entries, but entries 20-31 would be read-only-zero

The other option here is to allocate all 48 at once (and for your example 20-63 would be read-only-zero). This might be slightly easier for software portability and is neutral for HW cost.

 

 

What do people think?

👍

 

Tariq

 

Tariq Kurd

Processor Design I RISC-V Cores, Bristol

Tel: none I Mobile: +447711069063 I E-mail: Tariq.Kurd@...

Company: Huawei I Address: 160 Aztec West, Bristol, UK, BS32 4TU

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