Abner Chang <abner.chang@...>
Andrew, the intention of Configuration Structure task group is to define RISC-V core/hart hardware features in the configuration structure and retrieved by M-mode
software without probing the existence of features using exception.
How PMP structure is defined is not in the scope of Configuration Structure. However, the capability which is not defined in the privilege spec such as the number
of PMP entries (0, 16, 64) is good to defined in Configuration Structure, so does CLIC base address, ePMP, SPMP and etc..
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From: tech-privileged@... [mailto:tech-privileged@...]
On Behalf Of Andrew Waterman
Sent: Monday, May 25, 2020 12:07 PM
To: Chang, Abner (HPS SW/FW Technologist) <abner.chang@...>
Cc: Tariq Kurd <tariq.kurd@...>; tech-privileged@...
Subject: Re: [RISC-V] [tech-privileged] Extending the number of PMP entries
The situation hasn't changed: it has always been straightforward to write M-mode software to detect the number of PMP registers at runtime, relying on precise exceptions. IMO, that means this stuff doesn't belong in the configuration structure,
but lazier programmers disagree.
On Sun, May 24, 2020 at 7:53 PM Chang, Abner (HPS SW/FW Technologist) <abner.chang@...> wrote:
Just writing to confirm that there is no information regards to the # of PMP entries supported by hart
mentioned in privilege spec . If my understanding is correct, then this information is good to go to RISC-V configurations structure.
-
Abner
I've made a pull request to extend the number of PMP entries, and have attached the compiled PDF for convenience. Feedback and error detection are appreciated: the fact that there
used to be 16 PMP entries manifested in several places in the document.
Hi Andrew,
That’s fine for me. Implementing 0 / 16 / 64 PMP entries is ok
Tariq
From: Andrew Waterman [mailto:andrew@...]
Sent: 21 May 2020 17:50
To: Tariq Kurd <tariq.kurd@...>
Cc: tech-privileged@...
Subject: Re: [RISC-V] [tech-privileged] Extending the number of PMP entries
Hi everyone,
Can we allocate more CSRs so that we can have more PMP entries available? We already have one implementation which requires 20 PMP entries, for example.
Currently the CSR address space can allow up to 64 PMP entries (unless CSRs have been allocated which I don’t know about).
0x3A4 – 0x3AF could become pmpcfg4-15
0x3C0 – 0x3EF could become pmpaddr16-63
64 entries would be more than enough (I don’t envisage needing more than 32), but I don’t know about other users.
I’m happy to allocate the PMP entries in blocks of 16, for example, and make higher numbered unused entries read-only-zero to save area.
So in our case we would implement the CSRs for 32 entries, but entries 20-31 would be read-only-zero
The other option here is to allocate all 48 at once (and for your example 20-63 would be read-only-zero). This might be slightly easier for software portability and is neutral for
HW cost.
Tariq
Tariq Kurd
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