Re: Extending the number of PMP entries
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Mr Tariq Kurd <tariq.kurd@...>
Thanks for this Andrew, it’s really useful. My only comment is:
“Up to 64 PMP entries are supported. Implementations may implement zero, 16, or 64 PMP CSRs. All PMP CSR fields are WARL and may be hardwired to zero. PMP CSRs are only accessible to M-mode.”
Whether we should require people to only hardwire the highest numbered entries to zero. Otherwise, in theory, a discovery mechanism which checks which PMP CSRs are writeable will need to probe all of them, instead of starting at the highest number (15 or 63) and then probing downwards until it finds the first writeable one. So there should be one writeable block starting from 0 and optionally one read-only-zero block in the highest numbered entries only.
Tariq
From: Chang, Abner (HPS SW/FW Technologist) [mailto:abner.chang@...]
Sent: 25 May 2020 09:24 To: Anup Patel <anup.patel@...>; Andrew Waterman <andrew@...>; Tariq Kurd <tariq.kurd@...> Cc: tech-privileged@... Subject: RE: [RISC-V] [tech-privileged] Extending the number of PMP entries
Same understanding here Anup. The most of uses are runtime debug, trace, compliance validation and POST time firmware (configures H/W and also builds up DT for the software you mentioned).
Abner
From:
tech-privileged@... [mailto:tech-privileged@...]
On Behalf Of Anup Patel
You are free to add it in “RISC-V configuration structure” but from Linux, Hypervisors and M-mode RUNTIME firmware perspective we don’t’ need it.
All these software will:
Regards, Anup
From:
tech-privileged@... <tech-privileged@...>
On Behalf Of Abner Chang
Missed this mail while I was replying to Andrew. Same feedback to your comment in that reply.
From:
tech-privileged@... [mailto:tech-privileged@...]
On Behalf Of Anup Patel
This is not needed. We can easily probe number of PMP registers using illegal instruction traps. Look at latest OpenSBI sources.
Regards, Anup
From:
tech-privileged@... <tech-privileged@...>
On Behalf Of Abner Chang
Just writing to confirm that there is no information regards to the # of PMP entries supported by hart mentioned in privilege spec . If my understanding is correct, then this information is good to go to RISC-V configurations structure.
- Abner
From:
tech-privileged@... [mailto:tech-privileged@...]
On Behalf Of Andrew Waterman
I've made a pull request to extend the number of PMP entries, and have attached the compiled PDF for convenience. Feedback and error detection are appreciated: the fact that there used to be 16 PMP entries manifested in several places in the document.
On Fri, May 22, 2020 at 12:30 AM Tariq Kurd <tariq.kurd@...> wrote:
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