Appearance of new M-mode CSR bits when Hypervisor is disabled
The Hypervisor extension adds bits to some of the existing M-mode CSR's. When this extension is not implemented, these bits are hardwired to zero. When the extension _is_ implemented these bits become either read/write or (in a few cases) hardwired to one.
On the one hand the hypervisor spec says that when misa.H=0 (i.e. the extension is "disabled"), "the hart behaves as though this extension were not implemented". But where these various added M-mode CSR bits are described, they are defined to exist when "the hypervisor extension is implemented".
The former statement implies that these new bits must appear to be hardwired to zero when misa.H=0, while the latter statement implies that these new bits appear to be read/write or hardwired to one irrespective of misa.H (although presumably they have no functional effects when misa.H=0).
Which is the correct architectural intention?