I focused on the HW writes to mtval when I described the Rocket core's behavior to Allen.  The behavior for SW writes is that it unconditionally sign-extends from the most-significant implemented bit: in other words, the behavior that the MSBs are checked for a proper sign-extension only applies to HW writes.  This is a reasonable implementation, and in some respects a preferable one.  The purpose of the recoding is to provide information to SW.  Enforcing the same constraints on SW writes is arbitrary, and might even be detrimental in some virtualization cases.