Re: xTVAL Compliance restriction proposal

Andrew Waterman

On Tue, Jun 16, 2020 at 12:06 AM Greg Favor <gfavor@...> wrote:
On Mon, Jun 15, 2020 at 11:33 PM Andrew Waterman <andrew@...> wrote:
I focused on the HW writes to mtval when I described the Rocket core's behavior to Allen.  The behavior for SW writes is that it unconditionally sign-extends from the most-significant implemented bit: in other words, the behavior that the MSBs are checked for a proper sign-extension only applies to HW writes.  This is a reasonable implementation, and in some respects a preferable one.  The purpose of the recoding is to provide information to SW.  Enforcing the same constraints on SW writes is arbitrary, and might even be detrimental in some virtualization cases.

That sounds good.

It would be great to see this software write behavior added to the Priv spec (along with whatever hardware write behavior that Allen's polling concludes with).

Thanks for your input, as always.

I agree that, if we ultimately agree to tighten the behavior here, we need to specify the behavior for both HW and SW writes.


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