Re: mtvec question
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I think the solution is even simpler.
Even if MTVEC had not been used, data dependent traps are prohibited in Risc-V (that might be too strong a word; I don't know that its explicited prohibited, but certainly is discouraged for good reason)
Note that Divide by 0 doesn't trap, and if anything would trap, you would think that would be first in line.
Nevertheless - MTVEC[1:0] is WARL, and you can restrict the legal values as you see fit (that is, transform anything that is not legal into a legal value, which can include leaving the value unchanged) - but you cannot trap.
And, the implementation gets to decide what is legal.
Your implementation can declare that mtvec is read-only zero (and so won't support CLIC)
Your implementation can declare that attempts to write 10 or 11 will be ignored, or will be converted to the legal 00 and 01 or even always to 00, or declare that only 00 is legal (If you didn't support vectored interrupts) so it is read-only 0.
So you can prevent that case you're worried about fairly easily.
You could go further and restrict the address to be cache line aligned regradless of vectoring (so mtvec [5:2]=0; or page aligned (mtvec[11:2]=0) (see the last note in priv spec 3.1.7 that discusses this).
On Fri, Jun 19, 2020 at 12:01 AM Andrew Waterman <andrew@...> wrote: