Re: Appearance of new M-mode CSR bits when Hypervisor is disabled
Greg Favor wrote:
The Hypervisor extension adds bits to some of the existing M-mode CSR's.The overriding statement in the document is this one:
When misa (bit H) is clear, the hart behaves as though this
extension were not implemented, ....
I sympathize with the desire to enforce an intuitive view that, if
misa.H is writable and set to 0, the hypervisor extension really _is_
implemented, just disabled. However, I believe the statement above
is clear that when misa.H = 0, the hardware must act the same as when
the hypervisor extension is not implemented. If that statement didn't
override an intuitive interpretation of _implemented_ everywhere in the
chapter, then the statement would be null-and-void, and that can't be
Allowing "implementation" to be configurable at run-time may be
non-intuitive, but I claim the hypervisor chapter is consistent with
similar other uses in the document. For example, concerning the FS
field in mstatus, the document says:
In systems that do not implement S-mode and do not have a
floating-point unit, the FS field is hardwired to zero.
What about when misa.F and misa.S are both writable and set to zero?
In that case I believe the specification requires that mstatus.FS
be read-only zero, the same as when the F extension and S mode are
not implemented. So what does the document really mean by "do not
implement S-mode" and "do not have a floating-point unit"?
If anything, I think the hypervisor chapter is being slightly more
careful to document the consequences of modifying misa.
- John Hauser