Re: xTVAL Compliance restriction proposal

Greg Favor

On Tue, Jun 30, 2020 at 4:19 PM Allen Baum <allen.baum@...> wrote:
You said:
  Sign extend if translated
 Zero extend otherwise (I don’t think that’s is quite the same as Bare+Mmode because of MPRV, and not sure how hypervisor modes affect that)

One could view the effect of MPRV as changing the mode that is in effect for a memory access.  For *tval purposes that end result is all that matters.  Ditto for the new-ish HLV/HLVX/HSV instructions.

I don't think the new/added hypervisor VS/VU modes change much - since they are supposed to behave like S/U modes.

For two-stage translations what matters is the stage that is causing an exception and what that stage's translation mode is.

So I believe my admittedly terse statement is correct (albeit without all the extra verbiage describing these various cases).  It is the relevant and final/effective privilege/translation modes that matter.

Then you said that the extension would be from the highest address bit-  but if VA>PA, isn’t that effectively zero extending the PA even in bare mode? That seems to contradict the first statement.

I agree that if VA>PA, then always sign-extending from the implemented address msb works.  My statement was addressing the case of PA>VA - in which sign-extending is not always correct.


As usual, I’m probably interpreting something  which might be interpreted more than one way in exactly the wrong way- that is my superpower.  What am I getting wrong? Compliance wants to know!


On Jun 30, 2020, at 12:45 PM, Greg Favor <gfavor@...> wrote:

Coming back to designs where the implemented PA size is greater than the supported VA size (for example, 48b VA's and 50b+ PA's), and in contrast to always sign-extending when VA size is greater than PA size, the situation is a little more complicated when PA size is greater than VA size:

On hardware and software writes one wants to zero-extend if under M-mode or a Bare translation mode, or sign-extend if under a translated mode.  In other words that one extra storage bit is loaded with either zero or sign extension of the highest supported address bit.

Compliance testing should keep this class of scenarios (i.e. PAsize > VAsize) in mind.


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