The mcycle CSR is described in the RISC-V Privileged Architecture spec as:
The mcycle CSR counts the number of clock cycles executed by the processor core on which the hart is running.
What does 'clock cycles executed by the processor' mean in the context of a WFI instruction? For example, if a core is stalled on a WFI (waiting for e.g. an interrupt to become pending), should mcycle keep incrementing even if for example the remainder of the core's pipeline is clock gated?
