Re: A proposal to enhance RISC-V HPM (Hardware Performance Monitor)
- Is Active (bit) any different from the inhibit register, functionally speaking?
- Assume that we are making this HPM as an extension (maybe Zmhpm, Zshpm?). How is it possible that no extra registers are needed together with H Extention? At least we need the counteren.
- Did you implement this proposal into a solution that perf really works? As mentioned in the original post, we (Andes) released implementations both in hardware and software since two years ago.
The main difference between our proposal and yours is the way we implement the essential HPM functionalities. I resist the idea of overloading hpmevents purely because we have been working in the other way (adding CSRs) . After reviewing the existing code and the perf_event framework, I don't think there will be any trouble developing perf based on your proposal. Also thank you for covering H extension here.