Re: A proposal to enhance RISC-V HPM (Hardware Performance Monitor)
Thank you for the hints as an Intel PMU architect. My question is about the mode selection part as below.
It is not difficult to implement such a mechanism that an event should only be counted in some privileged modes. Both Greg's and my approach can achieve this. But in practice, we found profiling higher-privileged modes has some problems. Under basic Unix-like RISC-V configuration, the kernel runs in S-mode and there is M-mode for platform-specific stuff.
Says we now want to sample M-mode software. The first implement decision is which mode the HPM interrupt should go. Everything can be more controllable if the interrupt can just go S-mode, but obviously there is no easy way for S-mode software, the kernel, to read general M-mode information like mepc (Machine Exception Program Counter) register. The other route goes to M-mode, but since RISC-V HPM interrupt has never been seriously/publicly discussed until this thread, the effort so far including current PMU SBI extension proposal did not address this.
I am curious how x86 address this problem. How does it enable hypervisor mode sampling without similar issues?