Re: A proposal to enhance RISC-V HPM (Hardware Performance Monitor)
Few comments on your proposal (https://lists.riscv.org/g/tech-privileged/message/205):
1. The BIT is not required because we already have MCOUNTINHIBIT CSR
2. The BIT contradicts CSR number semantics of HPMCOUNTER CSR because currently all HPMCOUNTER CSRs are “User-Read-Only”.
3. We need to align “event_info” definition in SBI PMU Extension to consider your prosed bits in MHPMEVENT CSRs.
From: tech-privileged@... <tech-privileged@...> On Behalf Of Greg Favor
Sent: 30 July 2020 12:57
To: alankao <alankao@...>
Subject: Re: [RISC-V] [tech-privileged] A proposal to enhance RISC-V HPM (Hardware Performance Monitor)
I'm fine with taking the lead on this architecture extension. But it should follow a proper process as directed by the TSC. Thus far this would mean getting a new TG created or doing something less formally under an existing TG. But for smaller extension proposals like this there is need for a proper lighter weight and faster process. Need for this is recognized and I suspect will probably be promulgated by the TSC some time soon.
So I suggest we pause for a short bit, and then see if we can follow that expedited process once it is available. In the meantime I/we can prepare what we can in advance. (I don't think this will represent a material slow down to getting to a frozen spec and then to ratification.)
On Wed, Jul 29, 2020 at 5:24 PM alankao <alankao@...> wrote: