Re: A proposal to enhance RISC-V HPM (Hardware Performance Monitor)
Thanks. Comments below.
On Mon, Aug 3, 2020 at 9:25 PM Anup Patel <Anup.Patel@...> wrote:
This is up in the air for inclusion or not in the proposal. As solely a bit that software can set/clear to start/stop a counter, the argument for having this bit is weak. Although SBI calls for writing to the mhpmevent CSR for a counter would need some way to recognize when the associated bit in mcountinhibit needs to be set or cleared. But with this bit in mhpmevent itself, no special support is needed (i.e. the writing of event_info into the upper part of mhpmevent takes care of whatever all bits are there).
The argument for this bit in mhpmevent grows when one allows for hardware setting and clearing of the bit. For example, in response to a cross-trigger from the debug Trigger Module (e.g. to start counting when a certain instruction executed and to stop counting when another address is executed). Or to start/stop counting in response to another counter overflowing after N occurrences of some event. Currently cross-trigger capabilities like this aren't standardized but, irrespective of whether they get standardized or not, having a standard Active bit provides the framework for a design to have whatever mechanisms it desires.