Re: comments on PMP enhancements

Bill Huffman

Hello John,

I'm thinking positively about your proposal for a 2-bit MSL field and a
2-bit PL field per PMP entry. But I'm still a little concerned by what
you say below...

Chipmakers sometimes wish to include code in a memory region which is
set by boot code to be execute-only forever (until reset). They want to
do this so that even their customers, who do additional programming on
the chip - including in M mode - cannot read the chipmaker's code.

With the statements about MXR, MPRV, and MPP below, I think this can
only be accomplished for code executable in M mode only. I wonder if
there is a way it can be done for code executable in S/U mode.


On 2/11/20 8:48 PM, John Hauser wrote:

I wrote:
As Jonathan Behrens has already noted, some systems depend on being
able to set mstatus.MXR = 1 temporarily to read S/U-executable
instructions, for emulation purposes. The proposal should be modified
to say that any S/U-mode-only PMP region that grants execute permission
to S/U modes (bit X is set), implicitly grants read permission to
M mode when MXR = 1.
Correction: I believe that should say "... implicitly grants read
permission to S/U modes when in M mode and MXR = 1". This is relevant
only when MPRV = 1 and MPP = 0 or 1, so it's a rather narrow case.
Hopefully I've got it right this time.

- John Hauser

Join to automatically receive all group messages.