Re: comments on PMP enhancements
Hello John,toggle quoted message Show quoted text
I'm thinking positively about your proposal for a 2-bit MSL field and a
2-bit PL field per PMP entry. But I'm still a little concerned by what
you say below...
Chipmakers sometimes wish to include code in a memory region which is
set by boot code to be execute-only forever (until reset). They want to
do this so that even their customers, who do additional programming on
the chip - including in M mode - cannot read the chipmaker's code.
With the statements about MXR, MPRV, and MPP below, I think this can
only be accomplished for code executable in M mode only. I wonder if
there is a way it can be done for code executable in S/U mode.
On 2/11/20 8:48 PM, John Hauser wrote:
I wrote:2.Correction: I believe that should say "... implicitly grants read