Re: A proposal to enhance RISC-V HPM (Hardware Performance Monitor)
No issues with Bit of your proposed MHPMEVENT definition. The SBI_PMU_COUNTER_START/STOP calls can either update MCOUNTINHIBIT Bits or these calls can update Bit of appropriate MHPMEVENT CSR.
Regarding Bit, I agree with you. Let’s wait for more comments.
From: Greg Favor <gfavor@...>
Sent: 04 August 2020 11:40
To: Anup Patel <Anup.Patel@...>
Cc: alankao <alankao@...>; tech-privileged@...
Subject: Re: [RISC-V] [tech-privileged] A proposal to enhance RISC-V HPM (Hardware Performance Monitor)
On Mon, Aug 3, 2020 at 10:57 PM Anup Patel <Anup.Patel@...> wrote:
That reduces the argument for bit . I won't remove it yet (until I write up an updated proposal), but I imagine that bit will be dropped if no one else speaks up in support of it. (Although if/when someone (such as us) supports hardware events starting and stopping counters, then we'll have to deal with the fact that this is a change to the current arch definition of the mcountinhibit CSR.)
I'm OK with this. It is other people that have been more desirous of this feature. I agree that it would be cleaner and simpler to not have this bit, but let's see who speaks up for keeping this feature.