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  2. 答复: [RISC-V] [tech-privileged] RFC: Dedicated Clock Source and Clock Event Source for HS-mode and VS-mode

Re: 答复: [RISC-V] [tech-privileged] RFC: Dedicated Clock Source and Clock Event Source for HS-mode and VS-mode

Siqi Zhao
 

Thanks for the timely comment, we are aware of the htimedelta CSR in the hypervisor spec. Section 3 is meant to propose aliases available in VS-mode and VU-mode. Because they are meant to provide time for a virtual machine, the value returned should be adjusted by the htimedelta CSR. That sentence is meant to state this requirement.

 

发件人: Andrew Waterman [mailto:andrew@...]
发送时间: 2020年8月4日 15:34
收件人: zhaosiqi (A) <zhaosiqi3@...>
抄送: tech-privileged@...
主题: Re: [RISC-V] [tech-privileged] RFC: Dedicated Clock Source and Clock Event Source for HS-mode and VS-mode

 

Note that Section 3 of your proposal already exists.  The hypervisor spec says, "The htimedelta CSR is a read/write register that contains the delta
between the value of the time CSR and the value returned in VS-mode or VU-mode."  In other words, reading the time CSR when V=1 does what you propose.

 

On Tue, Aug 4, 2020 at 12:25 AM zhaosiqi (A) via lists.riscv.org <zhaosiqi3=huawei.com@...> wrote:

Hello Everyone,

 

We have come up with some ideas about improving the performance of virtual machines on the RISC-V architecture. Here’s the first piece which proposes a dedicated clock source and a clock event source for HS-mode and VS-mode, respectively. We extended the current idea of the mtime and mtimecmp CSRs and combined with the current hypervisor extension to come up with new CSRs and aliases. Evaluations on QEMU show that the proposed extension leads to performance improvement.

 

The attached document details the proposal. Any comments are welcome.

 

Regards,

Siqi
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