Re: A proposal to enhance RISC-V HPM (Hardware Performance Monitor)

Anup Patel

Hi Alan,


I think I am repeating myself here but still don’t see any benefit of allowing HPMCOUNTER CSR write access to S-mode. On the contrary, it will make context switching expensive for hypervisors.


The SBI PMU extension is designed such that kernel need not be aware of HS-mode or VS-mode. For Guest kernel (VS-mode), SBI is provided by Hypervisor so Hypervisor will act as mediator for Guest kernel. For Host kernel (HS-mode), SBI provider is M-mode runtime firmware (OpenSBI). The Linux PMU driver should not

care which mode it is running (HS-mode or VS-mode). The same rationale applies here, we use single Linux RISC-V kernel image for both Guest and Host.





From: tech-privileged@... <tech-privileged@...> On Behalf Of alankao
Sent: 05 August 2020 10:23
To: tech-privileged@...
Subject: Re: [RISC-V] [tech-privileged] A proposal to enhance RISC-V HPM (Hardware Performance Monitor)


Hi Anup,

> Linux PMU driver framework only updates counter value in “add()” or “start()” callback. That’s why allow S-mode write HPMCOUNTER CSRs won’t provide much benefit.

It doesn't matter where the kernel does the update.  What matters is how often kernel does add() and start().  Anyway, it may take a while but we will do the experiment mentioned in previous thread to give real evidence here.

> We should avoid a kernel feature which needs to be explicitly enabled by users and distros keeping it disabled by default. The “#ifdef” based feature checking should be replaced by runtime feature checking based on device tree OR something else.

Is there any way for a kernel to detect if it is in S-mode or VS-mode?  If so, then just don't go that route when writing HPM CSRs.  Just like what we did with CONFIG_FPU, I suggest we can set CONFIG_RESTRICT_HPM_REG_ACCESS or something true by default, and detect if there is some attribute like "bypass-sbi" in a PMU node.  With static key feature and the followups, this runtime check is not expensive.

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