Re: A proposal to enhance RISC-V HPM (Hardware Performance Monitor)
The “bypass-sbi” DT property will break QEMU virt machine for KVM because same QEMU virt machine is used with both TCG and KVM acceleration. This is yet another work-around for doing things differently for HS-mode and VS-mode in Linux PMU driver because kernel has no way of knowing which mode kernel is running (HS-mode or VS-mode).
The SBI_PMU_COUNTER_START() call can’t be by-passed because the bits which turn-on or turn-off counting are accessible to M-mode only. This SBI_PMU_COUNTER_START() call also takes counter start value provided by Linux PMU framework. We can easily write the counter start value in SBI implementation (M-mode runtime firmware) instead of writing it in S-mode. I still don’t see the benefit of directly writing counter value in S-mode.
From: tech-privileged@... <tech-privileged@...> On Behalf Of alankao
Sent: 05 August 2020 13:16
Subject: Re: [RISC-V] [tech-privileged] A proposal to enhance RISC-V HPM (Hardware Performance Monitor)
> I think I am repeating myself here but still don’t see any benefit of allowing HPMCOUNTER CSR write access to S-mode. On the contrary, it will make context switching expensive for hypervisors.