Simon Davidmann Imperas
We posted this on https://groups.google.com/a/groups.riscv.org/g/isa-dev/
but had no response in 2 weeks - so maybe this is a better place:
Looking forward to a response.
The Privileged Architecture specification describes special behavior for mip.SEIP as follows:
I think this description needs improvement, because the intent is not fully clear for SEIP, or other bits. In particular:
1. What about other set-pending bits that are writable by software? For example, if the N extension is implemented, how do mip.UEIP and sip.UEIP behave?
2. For which bits does any externally-asserted interrupt contribute to the result seen in rd for csrrc or csrrs? For example, would the external value of mip.SEIP contribute to rd in this case, or is just the software-writable bit value seen?
As a general case, imagine that:
1. A system using the N extension is being used;
2. All interrupts are delegated to their lowest possible privilege level using mideleg and sideleg;
3. All interrupts are disabled;
4. Interrupts MEI, SEI, UEI, MTI, STI and UTI are all asserted externally (so csrr t1, mip returns 0xbb0).
5. No software pending bits are set for these interrupts.
Given the above set up, what value is observed in t1 in each of these cases:
(Note that no CSR state is changed by these instructions - only the result in t1 is of interest.)
And given the same set up, which (if any) software-writable bits are set by these instructions:
li t0, 0
(In other words, what externally-asserted interrupt signal values are propagated to software-writable bits?)