Simon Davidmann wrote:
The Privileged Architecture specification describes special behaviorThe section you are quoting, 3.1.9, "Machine Interrupt Registers (mip
and mie)", says nothing about the N extension. If you look at the
figures for the mip register in that section, there is no UEIP bit
there. If the N extension's UEIP bit should have any special behavior,
the place for this to be specified would be the chapter on the
N extension, the same place where UEIP is first introduced.
As far as UEIP is concerned, I think your real complaint is that the
chapter on the N extension has never been completed or maintained.
I believe many of the principal movers are no longer interested in
developing or promoting this extension. For the N extension chapter to
be completed, somebody has to step up who wants this to be done. (My
own personal opinion is that we should drop the N extension.)
As to the bits of mip defined in section 3.1.9, I think the fact that
the document spells out a special case explicitly for SEIP and does not
do the same for any other bits in mip should be ample evidence that the
special case applies only to SEIP and not to any other bits defined for
mip in that section.
2. For which bits does any externally-asserted interrupt contributeThe value that a CSR instruction reads from mip into the instruction's
rd destination is not affected by which CSR instruction does the read,
whether it's CSRR, CSRRW, CSRRC, or CSRRS. In all cases, externally
asserted interrupts for bits MEIP and SEIP show up in the value written
to the rd destination.
As a general case, imagine that:As this question involves the N extension, I'll leave it others to say
how they think the N extension should be defined.
If you'd like to ask about a different example that doesn't involve the
N extension, I can try to answer.
- John Hauser