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Fair enough. Of course, your conclusion is totally correct: "we CAN EASILY set the HPM* ...," but the real question here is in point 1: Are counter updates really that in-frequent so? So far, nobody provided any convincing pieces of evidence. Yet, I would like to share our findings from an out-of-the-box experiment.
The system for testing is a 4.17-based Linux branch which contains andes_pmu patch, running on our A27 design on FPGA. The testing command was
time perf record -e cache-references ./whestone
where "cache-references" is an andes_pmu cache event and the target program is a normal whestone executable. We tested three different settings,
Baseline: all HPM CSRs are written in S-mode using plain csr_write.
SBI1: HPM counter CSRs are written with SBI calls.