1. posterid:1774265
  2. A proposal to enhance RISC-V HPM (Hardware Performance Monitor)

Re: A proposal to enhance RISC-V HPM (Hardware Performance Monitor)

Anup Patel
 

Hi Alan,

 

Like mentioned previously, having different mechanism for HS-mode and VS-mode to write HPMCOUNTER CSR is not acceptable. The “bypass-sbi” DT property only means that Linux PMU driver is now aware whether it is running natively or running inside Guest/VM. This is totally hacky and won’t be acceptable.

 

Regards,

Anup

 

From: tech-privileged@... <tech-privileged@...> On Behalf Of alankao
Sent: 18 August 2020 15:17
To: tech-privileged@...
Subject: Re: [RISC-V] [tech-privileged] A proposal to enhance RISC-V HPM (Hardware Performance Monitor)

 

Hi Anup,

We did the experiment based on our own settings and not yet consider the SBI extension proposal.

Please consider the approach in #278 with one additional condition: Any platform that supports configurations more than M-S-U should not provide a PMU with "bypass-sbi" attribute, like QEMU virt.  Neither VS- nor  HS- usage will be affected by this bit.  Then, you ask, what about emulating a platform that aims to only runs on M-S-U machines?  Well, the one who ports the platform to QEMU/other simulators should put some warning message when the attempt to write happens, rather than implement the whole save-restore just for the PMU status.

We don't need to add many CSRs.  Just one bit in hpmevent*.

Regards,
Alan

Join tech-privileged@lists.riscv.org to automatically receive all group messages.