Re: A proposal to enhance RISC-V HPM (Hardware Performance Monitor)
The fact that “write-enable” bit in HPMEVENT CSR makes corresponding HPMCOUNTER as writeable violates the RISC-V CSR numbering scheme of RISC-V privilege spec because it allows S-mode writing to a CSR from “User-read-only” range.
From: tech-privileged@... <tech-privileged@...> On Behalf Of Chuanhua Chang
Sent: 18 August 2020 15:35
Subject: Re: [RISC-V] [tech-privileged] A proposal to enhance RISC-V HPM (Hardware Performance Monitor)
The idea of adding write enable bit without adding extra CSR in the read/write register range is that the setting of the write enable bit will change the read-only CSR to a read/write CSR.