Re: A proposal to enhance RISC-V HPM (Hardware Performance Monitor)

Bill Huffman

On 8/18/20 8:19 AM, Chuanhua Chang wrote:

Hi, Anup,

Regarding the aspect of a "read-only" CSR, in the RISC-V PMP design, a control bit "L" in the pmpcfg CSR, once set, will change the corresponding read/write pmpaddr CSR to a "read-only" CSR.

They're not the same idea.  The PMP L bit changes the meaning of a write.  Rather than becoming a read-only register, it remains read-write, but writes behave differently and do nothing.  Registers with read-only numbers always take an exception on write.  The idea behind this is that exceptions do not depend on data in CSR registers to avoid difficult timing/layout issues.


So fundamentally, I do not see any reason why a control bit cannot change a "read-only" CSR to a "read/write" CSR. It should be similar to the above case in terms of implementation complexity.

And regarding the aspect of a "user" CSR, I also do not see any reason why a higher privileged mode such as S-mode cannot write to a user register, once the write permission is allowed by M-mode.


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