Re: A proposal to enhance RISC-V HPM (Hardware Performance Monitor)
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Well, I'd be a little bit more specific: access can be conditioned on more than the CSR number, as the existence of Mcounteren CSR proves.
But, in that case, the register bit that controls access is static, held in a CSR, not dynamic and selected by the instruction, as a GPR value would do.
On Thu, Aug 20, 2020 at 12:35 PM Bill Huffman <huffman@...> wrote: