Re: Proposal: Supervisor Timer CSR and Virtual Supervisor Timer CSR


Greg Favor
 

A few other small nits:

- Besides by S-mode and M-mode, the stimecmp CSR is accessible by HS-mode; and is accessible by VS-mode as well (during which the vstimecmp CSR contents substitute for stimecmp contents).

- The vstimecmp CSR is indirectly read/write accessible during VS-mode (as well as directly during M-mode and HS-mode).

- The *stimecmp CSR's are shown as having bits [11:0] and they are shown as TBD.  They instead should have the same format as mtimecmp, i.e. a full 64-bit unsigned value.

- Section 2.2 mistakenly says that "instructions that access stimecmp when V==0 access vstimecmp instead".  That should be for when V==1.

- From M/S/HS/VS modes, access to stimecmp does not trap.  But it does trap from U/VU modes.

- From M/S/HS modes, access to vstimecmp does not trap.  But it does trap from VS/U/VU modes.

- Lastly, what section 4 asks for, I believe is already provided via hideleg bit 6.

Greg




On Wed, Sep 2, 2020 at 8:24 PM zhaosiqi (A) via lists.riscv.org <zhaosiqi3=huawei.com@...> wrote:

Hi Everyone,

 

This is an updated version of our previous proposal on the clock source and clock event source. We have aligned our ideas with the latest hypervisor extension specs, removed the redundant parts, and uncovered some issues if we are going to implement this proposal with the current design. We give an analysis together with the proposed new CSRs in the attached document.

 

BTW, we have learned recently that there is an on-going work on an improved version of the PLIC which is virtualization-aware, is there any documents available?

 

Regards,

Siqi

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