Re: Proposal: Supervisor Timer CSR and Virtual Supervisor Timer CSR
Fair enough. I was thinking of a system where the DVFS would be under the control of M-mode software, but in some chips it could be done by a more autonomous DVFS controller of some sort.
Sounds like memory-mapped stimecmp/vstimecmp registers might be the best solution. I don't think anything in the existing spec would prevent this, but it would be nice to have it standardized (at least to the extent that mtime/mtimecmp are standardized...)