Re: rv(64) address space size

Andrew Waterman

It hasn’t been standardized yet, but there is a placeholder for the Sv57 encoding in the satp.MODE register field. There isn’t a chapter on the Sv57 spec, but it will follow the pattern of Sv39 -> Sv48, with one additional page-table level.

I will suggest to the virtual memory task group that we include Sv57 in the next batch of things we put up for ratification.

On Wed, Nov 25, 2020 at 2:15 PM swallach <steven.wallach@...> wrote:
is this documented?

much appreciated

On Nov 25, 2020, at 5:10 PM, Krste Asanovic <krste@...> wrote:

The basic design is already laid out for expansion to Sv57 and Sv64 following the template of fewer bits,

On Nov 25, 2020, at 1:15 PM, swallach <steven.wallach@...> wrote:

the current size of the virtual address space is 48 bits.  (per the june 2019 spec - volume II)

as many of you know,  INTEL has increased their address space to 57 bits.  several designers of server and hpc class of riscv systems  have  asked me about this.

so,  what is the current view on this.  will riscv support the a 57 bit logical address space.

with the newer class of NVM  being   implemented,  many systems are looking at directly addressing,  cluster-wide ALL of physlcal memory

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