Re: Fast-track "stimecmp / vstimecmp" extension proposal

Greg Favor

On Tue, Dec 1, 2020 at 6:49 PM Jonathan Behrens <behrensj@...> wrote:
In addition, when the TM bit in the mcounteren register is clear, attempts to read the stimecmp register while executing in S-mode will cause an illegal instruction exception.

Presumably this should say "attempts to read or write the stimecmp register..."?

Yes.  Thanks for catching that.  (And the same applies for vstimecmp.)


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