Performance Monitor Interrupts

Sanjay Patel <spatel@...>




I have some questions about the hpm CSRs.


  • There is a conspicuous lack of an interrupt associated with a counter overflow.  Are custom interrupts expected to be provided in a RISC-V implementation?
  • What model does Linux perf assume for the use of the monitors? Does a standard release not use interrupts and if so, is polling used instead?
  • An SBI interface would seem to be needed for Supervisor/Linux to set the events? Is there a standard call defined?


This link alludes to similar issues, but it also says RISC-V implementations exist w/o an interrupt capabilty.






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