Re: Performance Monitor Interrupts

Greg Favor

On Wed, Dec 9, 2020 at 1:25 PM Sanjay Patel <spatel@...> wrote:

I have some questions about the hpm CSRs.


  • There is a conspicuous lack of an interrupt associated with a counter overflow.  Are custom interrupts expected to be provided in a RISC-V implementation?
Fancy you should ask. :)  A fast-track extension is being put together (and going thru some pre-review by a couple of key people) and hopefully should be put to initial public review very soon.  That extension will strive to standardize generating interrupts on counter overflows.  But thus far the architecture says nothing about this topic and hence anything done today by implementations in this regard is custom (and an implementation is free to do whatever it wants).
  • What model does Linux perf assume for the use of the monitors? Does a standard release not use interrupts and if so, is polling used instead?
This overflow interrupt capability is a missing architectural feature that other architectures have, and Linux perf supports, and needs to be added to RISC-V to bring it on par with everyone else.  As far as what happens for RISC-V in Linux perf in this particular regard, I'll let a software person provide a proper answer.
  • An SBI interface would seem to be needed for Supervisor/Linux to set the events? Is there a standard call defined?
In today's architecture the hpmcounter CSRs and the associated mhpmevent CSRs can only be written in M-mode.  An OpenSBI extension is currently in progress of being added to OpenSBI to support setting of these CSRs by lower privilege modes.


Join to automatically receive all group messages.