Re: [EXTERNAL]Re: [RISC-V] [tech-privileged] Performance Monitor Interrupts

Sanjay Patel <spatel@...>

(+platforms, which Mark had added in.)

Thanks for the quick reply Greg. Good to know it is of concern to others. 馃槉

I assume the specification will be posted for public review in the privileged workgroup. Is there an approximate timeline?


From: Greg Favor <gfavor@...>
Date: Wednesday, December 9, 2020 at 2:09 PM
To: Sanjay Patel <spatel@...>
Cc: "tech-privileged@..." <tech-privileged@...>
Subject: [EXTERNAL]Re: [RISC-V] [tech-privileged] Performance Monitor Interrupts

On Wed, Dec 9, 2020 at 1:25 PM Sanjay Patel <spatel@...> wrote:

I have some questions about the hpm CSRs.

聽聽聽聽聽聽聽聽 There is a conspicuous lack of an interrupt associated with a counter overflow.聽 Are custom interrupts expected to be provided in a RISC-V implementation?

Fancy you should聽ask. :)聽 A fast-track extension is being put together (and going thru some pre-review by a couple of key people) and hopefully should聽be put to initial聽public review very soon.聽 That extension will strive to standardize generating interrupts on counter overflows.聽 But thus far the architecture says nothing about this topic and hence anything done today by implementations in this regard is custom (and an implementation is free to do whatever it wants).


聽聽聽聽聽聽聽聽 What model does Linux perf assume for the use of the monitors? Does a standard release not use interrupts and if so, is polling used instead?

This overflow interrupt capability is a missing聽architectural聽feature that other聽architectures have, and Linux perf supports, and needs to be added to RISC-V to bring it on par with everyone聽else.聽 As far as what happens for RISC-V in Linux perf in this particular regard, I'll let a software person provide a proper answer.


聽聽聽聽聽聽聽聽 An SBI interface would seem to be needed for Supervisor/Linux to set the events? Is there a standard call defined?

In today's architecture聽the hpmcounter CSRs and the associated mhpmevent CSRs can only be written in M-mode.聽 An OpenSBI extension is currently in progress of being added to OpenSBI to support setting of these CSRs by lower privilege modes.


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