Re: [EXTERNAL]Re: [RISC-V] [tech-privileged] Performance Monitor Interrupts
Sanjay Patel <spatel@...>
(+platforms, which Mark had added in.)
Thanks for the quick reply Greg. Good to know it is of concern to others. 😊
I assume the specification will be posted for public review in the privileged workgroup. Is there an approximate timeline?
From: Greg Favor <gfavor@...>
On Wed, Dec 9, 2020 at 1:25 PM Sanjay Patel <spatel@...> wrote:
Fancy you should ask. :) A fast-track extension is being put together (and going thru some pre-review by a couple of key people) and hopefully should be put to initial public review very soon. That extension will strive to standardize generating interrupts on counter overflows. But thus far the architecture says nothing about this topic and hence anything done today by implementations in this regard is custom (and an implementation is free to do whatever it wants).
This overflow interrupt capability is a missing architectural feature that other architectures have, and Linux perf supports, and needs to be added to RISC-V to bring it on par with everyone else. As far as what happens for RISC-V in Linux perf in this particular regard, I'll let a software person provide a proper answer.
In today's architecture the hpmcounter CSRs and the associated mhpmevent CSRs can only be written in M-mode. An OpenSBI extension is currently in progress of being added to OpenSBI to support setting of these CSRs by lower privilege modes.