Your SATPU and SATPK registers seem to each contain: 64-bits of PPN, 32-bits of ASID, 4-bits for MODE and 28-bits reserved. But that adds up to 128-bits which is double the size of CSRs on 64-bit RISC-V processors. Are you imagining that RV57K would require a 128-bit processor, or am I misunderstanding something?

Jonathan

On Fri, Jan 29, 2021 at 10:31 AM swallach via lists.riscv.org <steven.wallach=bsc.es@...> wrote:

attached is a proposal for the definition of RV57K.  RV57K is an extension to  RV57.  the main extension is to incorporate two HARDWARE registers.  These registers are used to partition user and kernel address spaces.  Additionally the higher order address bit signifies user/kernel space.  This definition was discussed at length in the sigHPC group. applications that are hosted on these class of systems,  especially going forward,   expect secure environment with peta bytes of data.  of course there are 10,000 (or more) compute nodes. The basis for the proposed RV57K is KASLR effort, Thus there are Linux ports that adhere to this definition.  Most of the feature set proposed,  is already available in ARM based implementations. RV57K DOES NOT necessarily replace RV57.  

as noted,  this is just the beginning.  once approved,  we will move to defining RV64.  Currently,  to the best of my knowledge,  there is no definition of a RV64 like addressing structure, as least for the IA-64. within the sigHPC group we are anticipating the requirements of EXASCALE COMPUTING.  One of the most obvious requirements will be an Exascale of distributed main memory.

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