Re: RISC-V H-extension freeze consideration
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-----Original Message-----From hypervisor perspective, the "G" bit in G-stage PTEs is not used at all. For software emulated MMIO, the hypervisor does not create any mapping in the G-stage to ensure that it always traps which allows hypervisor to trap-n-emulate it. For pass-through MMIO (such as IMSIC guest MSI files directly accessed by Guest), the guest physical address translates to host physical address of actual MMIO device in the G-stage and we will have host PMAs which will mark all MMIO devices as IO regions. At this point, the G bit in the G-stage PTE is unused from software perspective. Why do we need to re-purpose G-bit because we already have PMAs marking all MMIO addresses as I/O region ? Regards, Anup
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