- [RISC-V] [tech-unixplatformspec] RISC-V H-extension plus RISC-V AIA proof-of-concept completed
Re: [RISC-V] [tech-unixplatformspec] RISC-V H-extension plus RISC-V AIA proof-of-concept completed
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let's create a top sheet and add this please. philipp is working on a review proposal. likely more like tech-announce for 2 weeks and notify TSC and the board. etc
The KVM RISC-V AIA support has been successfully validated with
AIA IMSIC virtualization features emulated by QEMU RISC-V.
This means KVM RISC-V Guest Linux works perfectly fine with Guest
VCPUs accessing VS-level IMSICs mapped in the G-stage page table.
Using VS-level IMSICs, the VCPUs of a KVM Guest are able to directly
inject IPIs without involvement of hypervisor (i.e. no MMIO trap or
SBI IPI calls) and there are no traps (or VM exits) involved in handling
external interrupts inside KVM Guest.
This also means guest external interrupt support CSRs (i.e. HGEIE,
HGEIP, and HSTATUS CSRs) of RISC-V H-extension are functionally
complete and no changes are required in RISC-V H-extension to
support virtualization aware external interrupt controllers (such
as AIA IMSICs).
This is a major milestone for both RISC-V H-extension and RISC-V
AIA specifications. It also satisfies the RISC-V H-extension freeze
dependency on RISC-V AIA proof-of-concept implementation.
There will be demo of KVM RISC-V AIA support in next AIA meeting
so stay tuned.
Meanwhile, people who want to try KVM RISC-V AIA can refer
1) QEMU RISC-V with AIA support is in riscv_aia_v2 branch of
2) KVMTOOL RISC-V with AIA support is in riscv_aia_v1 branch of
3) KVM RISC-V with AIA support is in riscv_kvm_aia_v1 branch of
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