When Physical Address Size < XLEN, should address check be performed on unused upper address bits?

Ricardo Ramirez

In RISC-V, instruction fetch addresses and load and store effective addresses are XLEN bits wide; however, an implementation can have a smaller physical address size.

When a core is in M-mode or Bare translation mode and the PA size < XLEN, what is the expectation on how the upper unused address bits are handled in regards to address checking? Is there an expectation from software?

For example, should h/w fault if the upper bits are not all 0 or an extension of the PA msb, or can the core simply ignore those bits?


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