Re: Fast-track "stimecmp / vstimecmp" extension proposal

Paul Donahue

I believe that stimecmp is intentionally defined to compare against the time CSR, not against the mtime memory-mapped register.



On Mon, Sep 13, 2021 at 12:49 PM Phil McCoy <pnm@...> wrote:

Was any consideration given to the possibility of defining stimecmp as a memory-mapped register (like mtimecmp) rather than a CSR?
Assuming that the timer will actually be implemented in a block outside of the CPU (e.g. the ACLINT), a memory-mapped register would be preferable for interfacing the CPU to the timer block.  Keep in mind that in most high-end (especially multi-processor) systems will have the timer in a separate clock domain from the CPU and CSRs (which seems to have been the key motivation for defining mtime/mtimecmp as memory-mapped registers rather than CSRs).

Also, just curious about the overall status of this extension.  It is mentioned in the RVA22 profile, which would suggest that the Sstc definition should be finalized soon if it isn't already.

Phil McCoy

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