Re: [RISC-V] [tech-tee] TEE proposal for M-mode SMEP/SMAP via PMP


Nick Kossifidis
 

Hello Greg and thanks for your feedback !

Στις 2019-12-21 05:04, Greg Favor έγραψε:
This all looks very good, except for one issue with item 3b: "Adding a
new PMP rule with pmpcfg.L and pmpcfg.X bits set fails with Security
exception."
RISC-V architecture - rather nicely - currently avoids having any
"register-operate" instructions that cause architectural exceptions
based on data-dependent execution (e.g. based on the value of its
register operands). Currently all computational instructions and CSR
rd/wr instructions conform to this. In contrast, item 3b violates
this and would represent the first and only case in which
implementations have to signal an exception on a "register-operate"
instruction at execution time (versus based on what can be checked at
decode time).
If people agree that this is undesirable, then it seems like the
suggested alternative or "fix" to this would be that the write to a
pmpcfg CSR write with pmpcfg.L and pmpcfg.X bits set, would not be
performed (i.e. the write is ignored and the register remains
unchanged). If desired, one could imagine things like also setting
some form of "security error" bit in the new mseccfg CSR.
Greg
Good point, I've updated the document so that writing pmpcfg.L and pmpcfg.X while MML is set is ignored. We could signal this in a different way but I don't think it's worth the complexity. Initially I thought that raising an exception will alert software about the illegal operation it tried to perform but it can simply read back the register to verify that.

Regards,
Nick

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