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On 29/10/21, 5:19 AM, "tech-privileged@... on behalf of Vedvyas Shanbhogue" <tech-privileged@... on behalf of ved@...> wrote:
> Yes. This was discussed before with Greg. This issue can be avoided by
> allowing other programmable counters (hpmcounter3-31) monitor the
> instret/cycle event as well.
> The current implementation in Qemu already supports this workaround.
I do not think it avoids the issue but works around it. Its not an
ideal workaround as the performance analyst now loses some of the
programmable performance counters...
Programmable counters would be more expensive to build and this places
pressure on those limited resources.
[Anup] I agree this is not an ideal work-around.
[Anup] I think the fast-track extension for CYCLE and INSTRET filtering
should be straight forward (i.e. defines only two CSRs) because most of
counter filtering functionality is already defined by Sscofpmf extension.
[Anup] I suggest Greg (or someone else) can just propose a write-up
for this fast-track extension.