Re: Questions on HPMs
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Fair enough. But it would be nice to have the full definition of instret in one place. To discern that instructions that cause exceptions don't increment the counter requires reading the ECALL/EBREAK description. Perhaps the following change would be reasonable:
M-mode includes a basic hardware performance-monitoring facility. The mcycle CSR counts the
number of clock cycles executed by the processor core on which the hart is running. The minstret
CSR counts the number of instructions the hart has retired. The mcycle and minstret registers
have 64-bit precision on all RV32 and RV64 systems.
========== NEW non-normative text ==========
Instructions that cause synchronous exceptions, including ECALL and EBREAK, are not considered to retire and hence do not increment the minstret CSR.
On Fri, Oct 29, 2021 at 9:57 AM Greg Favor <gfavor@...> wrote: