Hi Privileged ISA group,

There's been a longstanding shortcoming in the RISC-V Privileged ISA
document that it doesn't precisely explain what may happen when one
CSR controls the writability of bits or fields of a second CSR, and
the bits/fields of the second CSR are first configured as writable
(unmasked), then read-only (masked, usually zeros), then later back
to writable again. Is the original state of the second CSR retained
while the CSR bits/fields are masked and then revealed again by the
unmasking? Do writes to the second CSR while masked change this hidden
state? The current document rarely says.

To resolve these questions, a new subsection for the CSRs chapter is
proposed with the text below, or something to the same effect. My
interest for the moment is less to quibble over the exact words but
rather to give everyone an opportunity to comment on the intent,
assuming that much is clear. The current plan is to treat hidden,
masked state usually the same way that bit 1 of CSR epc is already
explicitly treated when IALIGN is configurable between 16 and 32 (for
example, because misa.C is writable).

The justification for keeping the hidden state is that this is usually
the cheapest for the hardware to implement---the same justification
there was for bit 1 of epc. Writes to the CSR's flip-flops can
continue to occur unchanged whether the CSR is masked or not; only the
flip-flops are ignored while the CSR is masked.

Be aware, there will be a number of deviations that will be necessary,
falling under the category of "specified otherwise". But we are
intending to have deviations only when needed.

Thoughts?

- John Hauser


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section title: Masking of CSRs and CSR Fields

The value written to one CSR may change whether the contents of a
second CSR, or a subfield of a CSR, is writable or read-only. In such
cases, unless specified otherwise:

- When the second CSR or subfield is configured as read-only, its
register state continues to exist but is said to be _masked_
(hidden).

- While the second CSR or subfield is configured as read-only, writes
to that CSR modify the masked register state as though the CSR or
subfield were configured as writable. If the CSR or subfield is
WARL when writable, the value attained by the masked register state
is always a valid one, the same as if the CSR or subfield were
configured as writable.

- When a write to the first, controlling CSR changes whether the
second CSR contents or subfield is writable or read-only, the
corresponding register state becomes masked or unmasked accordingly
but its value is unchanged.

Masked register state is normally ignored for all other purposes, so
only the readable value of a CSR matters. Consequently, so long as a
CSR or subfield remains configured as read-only, any masked register
state that exists for it will have no visible effect.