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Re: [RISC-V] [security] Add a topic for today's Runtime-Sig meeting

Dong, thank you! this is great. let's make sure as the TG get started that all proposals and POCs get a chance to present their ideas. Also note as a reminder that a number of previous TGs have had

By mark · #1297 ·

Instret & Cycle Privilege Mode Filtering fast-track ISA extension review

Hi all, The ARC recently approved the Instret & Cycle Privilege Mode Filtering (Zicntrpmf) ISA extension to be pursued as a fast-track extension. This extension allows the instret and cycle counters

By Beeman Strong · #1296 ·

ARC (Architecture Review Committee) minutes for the week of 2/21/23

Zicond (fast-track): The last PR - to move the DVI text from non-normative to normative text (plus any other last edits) - is to be created shortly by the ARC. After which Zicond should be ready to

By Greg Favor · #1295 ·

Architecture Review Committee meeting minutes, Feb 14

WFMI instruction - The ARC discussed whether the current draft proposal for a WFMI instruction (Wait For "My" Interrupt) had any significant issues for virtualization. The committee concluded it

By John Hauser · #1294 ·

Re: Zicsr and mcountinhibit

The relevant passage in the Unpriv spec is actually: When any instruction executes, it implicitly reads mcountinhibit to decide whether to increment instret. That implicit read happens in program

By Greg Favor · #1293 ·

Re: Supervisor Counter Delegation fast-track ISA extension

Yes, good point, I would not expect that to be part of the ultimate spec.

By Beeman Strong · #1292 ·

Re: Supervisor Counter Delegation fast-track ISA extension

Shouldn't the whole "Usage" section be a non-normative comment?

By Phil McCoy · #1291 ·

Supervisor Counter Delegation fast-track ISA extension

Hi all, The ARC recently approved the Supervisor Counter Delegation ISA extension to be pursued as a fast-track extension. This extension allows M-mode software to allow select Zicntr and/or Zihpm

By Beeman Strong · #1290 ·

Zicsr and mcountinhibit

Hi all, Consider the following code sequence, assuming that mcountinhibit.IR has initial value 1: csrc mcountinhibit, 0x4 # uninhibit instret csrs mcountinhibit, 0x4 # inhibit instret My read of the

By Beeman Strong · #1289 ·

Re: [RISC-V] [tech-unprivileged] ARC (Architecture Review Committee) minutes for the week of 2/7/23

Thanks, Andrew and Greg, for your feedback. I understand that is not ARC's official responsibility, but it's always good to get opinions on that from ARC as well as timelines. I also agree it's

By Aaron Durbin · #1288 ·

Re: [RISC-V] [tech-unprivileged] ARC (Architecture Review Committee) minutes for the week of 2/7/23

Now that I have a chance, I was going to respond similarly. I would only add that at this very early stage in the process for a new arch extension, the ARC doesn't worry about how it may fit into

By Greg Favor · #1287 ·

Re: [RISC-V] [tech-unprivileged] ARC (Architecture Review Committee) minutes for the week of 2/7/23

I'm not speaking on behalf of the entire committee, but my take is that these are the kind of instructions that would be most useful if mandated by an RVA profile. It's hard to see them making the

By andrew@... · #1286 ·

Re: [RISC-V] [tech-unprivileged] ARC (Architecture Review Committee) minutes for the week of 2/7/23

Does the AR committee have an opinion on how those new instructions will surface in a Profile? i.e. RVA23? Or beyond?

By Aaron Durbin · #1285 ·

ARC (Architecture Review Committee) minutes for the week of 2/7/23

Vector Crypto: Received and starting to review final draft with hopes to finalize next week. IOMMU: After receipt of the final draft of the spec, review has been completed and AR approval has been

By Greg Favor · #1284 ·

Re: SFENCE.VMA/SINVAL.VMA and page faults

The spec mentions that implementations are permitted to ignore rs1 altogether, so trapping is certainly not required.

By andrew@... · #1283 ·

SFENCE.VMA/SINVAL.VMA and page faults

Greetings ! I understand that the SFENCE.VMA/SINVAL.VMA instructions have unspecified behavior if a non-canonical form virtual address is specified and specifically no page fault is expected. I

By Ved Shanbhogue · #1282 ·

Architecture Review Committee meeting minutes, 1/31/23

IOMMU: We await an updated draft and hope to provide final review very soon. Zc*: Recently proposed names for the new instruction formats have been approved with light modification. WFMI: The question

By andrew@... · #1281 ·

ARC (Architecture Review Committee) minutes for the week of 1/24/23

Zicond (fast-track): Final encodings were approved. PR's are being created to provide selected edits to the extension description and to move the DVI text from non-normative to normative text. The

By Greg Favor · #1280 ·

Re: Requirements on implementing cycle/instret/hpmcountern

I agree. Bottom line is we need the spec owner to chime in and ideally update the spec so it is more clear which will prevent further questions down the road, hopefully reducing the spec owners

By Jeff Scott · #1279 ·

Re: Requirements on implementing cycle/instret/hpmcountern

I note Spike goes for the occasionally update time shadow value via a backdoor option I brought up in my reply to Nick:

By Greg Chadwick · #1278 ·

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