Is RISC-V already facing a shortage of CSRs?

A few more points: Instead of linear CSR expansion 4-8-? CSRs, should the mechanism provide for a future transition to an indirect state space? That would need perhaps just two registers for address

Is this meaningfully different from what's now in the priv spec? In "Machine ISA Register misa": > When software enables an extension that was previously disabled, then all state uniquely

In our research N extension can speed up asynchronous operating system designs. It can run executor environments and tell them when the kernel need them to handle interrupts or raise signals. That may

I don't think the spec was ever updated accordingly. The issue was kept open as a placeholder until the spec change was proposed and written.

I found this thread implying that certain SYSTEM opcodes are available for defining custom instructions: https://github.com/riscv/riscv-isa-manual/issues/385 I didn't find any statement about this in

While I don't have a strong opinion on N-mode as such, I do worry a bit about being a follower, though not because being a follower is pejorative. I'd be more concerned that just following may not be

| On Mon, May 31, 2021 at 11:17 AM John Hauser <jh.riscv@...> wrote: | There is nothing novel about the situation I'm describing.  I'm certain | that hypervisors have emulated such

NVMe accommodates Submission Queues to be in either host or controller memory. Current RISC-V statements dictate that controller memory must be I/O, instead of the otherwise optimal Memory [this is

I believe the proposed change is not backward compatible. An implementation that writes the reserved combinations but faults all accesses to the region changes from legal to illegal, right?

To clarify, I didn’t mean WARL – you can’t do this to the page tables. But will combining the 3 bits into 1 single field make any sense? Regards, Freddie

On a related thought, should the same be applied to the PTE’s RWX bits? Regards, Freddie

That sounds familiar, but perhaps we never actually acted upon it. This time, I've made a PR here: https://github.com/riscv/riscv-isa-manual/pull/658

I thought that I had pointed this out quite a while ago and also thought that the RWX field had been updated to be a single 3bit WARL field. If each bit is individually a WARL field, then it is quite

... Another suggestion would be for an interested group of people to form an official SIG to pursue this area of ideas and innovation. SIGs have more flexibility to explore an area of interest

First and foremost, I apologize to Gernot and to the list. My little rant occurred in a heated moment of frustration with a few things (not related with Gernot or this topic). It was quick venting

TLDR: just tunnel under the "wall of words" to the recommendation below. This is hardly the hill for any of us to die on, especially by the hand of our fellow enthusiasts.

Can I just observe and complain a little that Gernot has been arguing for the N extension - but apparently doesn't know squat about its details. Questioning is fine, but the last thing we need are

On 6 Jun 2021, at 12:22, Jonathan Behrens <behrensj@...> wrote: OK, if that’s the case then it is of pretty limited use indeed. Gernot

Wouldn't you also want to isolate different interrupt handlers from each other and from any non-interrupt handler user code running on the system? With the N-extension itself none of that would be