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Re: SYSTEM opcodes available for custom instructions

I don't think the spec was ever updated accordingly. The issue was kept open as a placeholder until the spec change was proposed and written.

By andrew@... · #694 ·

SYSTEM opcodes available for custom instructions

I found this thread implying that certain SYSTEM opcodes are available for defining custom instructions: https://github.com/riscv/riscv-isa-manual/issues/385 I didn't find any statement about this in

By James Robinson · #693 ·

Re: [RISC-V] [tech-tee] [RISC-V] [tech-privileged] Proposed deprecation of N extension

While I don't have a strong opinion on N-mode as such, I do worry a bit about being a follower, though not because being a follower is pejorative. I'd be more concerned that just following may not be

By Allen Baum · #692 ·

Re: RISC-V H-extension freeze consideration

| On Mon, May 31, 2021 at 11:17 AM John Hauser <jh.riscv@...> wrote: | There is nothing novel about the situation I'm describing. I'm certain | that hypervisors have emulated such

By Krste Asanovic · #691 ·

Re: RISC-V H-extension freeze consideration

NVMe accommodates Submission Queues to be in either host or controller memory. Current RISC-V statements dictate that controller memory must be I/O, instead of the otherwise optimal Memory [this is

By Josh Scheid · #690 ·

Re: Seeking clarification on PMP behavior when R=0, W=1

I believe the proposed change is not backward compatible. An implementation that writes the reserved combinations but faults all accesses to the region changes from legal to illegal, right?

By Bill Huffman · #689 ·

Re: Seeking clarification on PMP behavior when R=0, W=1

To clarify, I didn’t mean WARL – you can’t do this to the page tables. But will combining the 3 bits into 1 single field make any sense? Regards, Freddie

By Xinhao (Freddie) Qu · #688 ·

Re: Seeking clarification on PMP behavior when R=0, W=1

On a related thought, should the same be applied to the PTE’s RWX bits? Regards, Freddie

By Xinhao (Freddie) Qu · #687 ·

Re: Seeking clarification on PMP behavior when R=0, W=1

That sounds familiar, but perhaps we never actually acted upon it. This time, I've made a PR here: https://github.com/riscv/riscv-isa-manual/pull/658

By andrew@... · #686 ·

Re: Seeking clarification on PMP behavior when R=0, W=1

I thought that I had pointed this out quite a while ago and also thought that the RWX field had been updated to be a single 3bit WARL field. If each bit is individually a WARL field, then it is quite

By Allen Baum · #685 ·

Re: [RISC-V] [tech-tee] [RISC-V] [tech-privileged] Proposed deprecation of N extension

... Another suggestion would be for an interested group of people to form an official SIG to pursue this area of ideas and innovation. SIGs have more flexibility to explore an area of interest

By Greg Favor · #684 ·

Re: [RISC-V] [tech-tee] [RISC-V] [tech-privileged] Proposed deprecation of N extension

First and foremost, I apologize to Gernot and to the list. My little rant occurred in a heated moment of frustration with a few things (not related with Gernot or this topic). It was quick venting

By Greg Favor · #683 ·

Re: [RISC-V] [tech-tee] [RISC-V] [tech-privileged] Proposed deprecation of N extension

TLDR: just tunnel under the "wall of words" to the recommendation below. This is hardly the hill for any of us to die on, especially by the hand of our fellow enthusiasts.

By David Horner · #682 ·

Re: [RISC-V] [tech-tee] [RISC-V] [tech-privileged] Proposed deprecation of N extension

Can I just observe and complain a little that Gernot has been arguing for the N extension - but apparently doesn't know squat about its details. Questioning is fine, but the last thing we need are

By Greg Favor · #681 ·

Re: [RISC-V] [tech-tee] [RISC-V] [tech-privileged] Proposed deprecation of N extension

On 6 Jun 2021, at 12:22, Jonathan Behrens <behrensj@...> wrote: OK, if that’s the case then it is of pretty limited use indeed. Gernot

By Gernot <gernot.heiser@...> · #680 ·

Re: [RISC-V] [tech-tee] [RISC-V] [tech-privileged] Proposed deprecation of N extension

Wouldn't you also want to isolate different interrupt handlers from each other and from any non-interrupt handler user code running on the system? With the N-extension itself none of that would be

By Jonathan Behrens <behrensj@...> · #679 ·

Re: Proposed deprecation of N extension

The thread model is any attacks on buggy software, and the defence has been known for 45 years: Satzer & Schroder’s Principle of Least Privilege. This means a highly modularised system with almost

By Gernot <gernot.heiser@...> · #678 ·

Re: Proposed deprecation of N extension

Is there a solution for an M+S+U (non bare S) implementation which contains a CLIC and desires high performance entry into the handler code while also limiting the handlers ability to access memory or

By Richard Bohn · #677 ·

Re: Proposed deprecation of N extension

Στις 2021-06-05 05:29, Gernot έγραψε: If we treat N extension as a security-related mechanism, the threat model it tries to address is not clear. Anything that can be done with the N

By mick@... · #676 ·

Re: Seeking clarification on PMP behavior when R=0, W=1

Thank you for the clarification. I can see now that it doesn't particularly matter which legal encoding is generated when writing the reserved value since it would be the responsibility of the

By James Robinson · #675 ·

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