>In particular, a portion of a misaligned store that passes the PMP check may become visible, even if another portion fails the PMP check I had no idea this was in the spec - so I'm glad you added

There are at least 3 potential boundaries: MMU pages, PMP regions, and PMA regions. All bytes of an access must be contained within a single PMP region. The operative word there is "access", because a

The ACTs will test that bits above b38 match b38 if SV39 is enabled Likewise for SV48 and SV 57. There is no SV64 yet, so any VA bits above b56 that don't match b56 are expected to always trap. If a

That could be ok for accesses to idempotent memory, but would likely be problematic for a non-idempotent location (e.g. a memory-mapped I/O register), and byte accesses to a word MMIO register might

It would be nice if it was architecturally defined/permitted for such straddling accesses to be performed a byte at a time. That makes the trap and emulate handler easier to code. If not a byte at a

| Can a virtual paged be mapped to addresses that cross PMA regions? For example, is it acceptable to map a 1GB page such that half its physical addresses have the (e.g.) cacheable | attribute

The PMA architecture allows a lot of implementation flexibility - including for example having small 4B regions. In that example one could easily have one 4KB page overlap multiple PMA

I'm getting there Andy. We have picked this back up recently and had a few meetings on it. How many years has it been? Too bloody many, but this will end this year. That sort of thing happens when I

This is a now active effort again in the J group. Derek has led discussions on selected aspects in some of the recent meetings. Greg

Derek, what's the status of taking your slides and turning them into an architecture spec? Who is actually doing that? How many years has it been already? __________________________________ |

I cannot say what the RISC-V rule is but I can provide example use cases for similar issues from other architectures. (1) Legacy MMIO map (2) non-legacy MMIOmap with huge, larger and larger pages /

OK Guy, I agree, let's try to move this forward. For that to happen you're going to need to do a fair amount of reading. Smiles, I've been anything but opaque on this subject, please see the attached

Folks -- This email thread is getting long and my inbox is getting full. I suggest that interested parties get the J group's proposal slide deck from Derek, and frame their questions and needs

Hi Guy, thanks for the email thread. Very interesting. I am hoping to get a precise understanding of 1) Your high level need, and 2) The details of the semantics you are asking for. I do need to say

Guy -- Have you read Derek's slide deck that he prepared for the J group on this? I believe it contains the answers and solutions that you are looking for. -- John

Hello, There is something unclear to me after reading the PMA section or the Privileged ISA manual (i.e. Section 3.6). Can a virtual paged be mapped to addresses that cross PMA regions? For example,

Derek, let's try to move the discussion forward instead of just back and forth. If the J extension will solve this problem, please describe how? You've been very opaque -- is that because it hasn't

Thank you for this email Guy. It clarifies many things. From: Mark Himelstein <markhimelstein@...> Sent: Thursday, August 11, 2022 9:01 AM To: tech-cmo@... Group Moderators <tech-cmo@...>; Guy

Thanks again to everyone! These answers make sense to me.

My earlier statement about PAs conceptually or architecturally being viewed as zero-extended values makes them agnostic to implemented PA size. In general, and irrespective of where a PA comes from