My interpretation of this is if a misaligned store crosses between two PMP regions, both of which allow the write it's permissible for the implementation to allow both of those writes to occur,

Interesting. I agree with Scott. It says "The matching PMP entry must match all bytes of an access" and "misaligned loads, stores, and instruction fetches may also be decomposed into multiple

I actually think that Oded has it right. IF the access fails because it crosses a PMP boundary - it's an illegal access fault. The trap handler could decompose that into two separate transactions,

I’m not sure I follow your response, Oded, but I believe the “decomposed” text in the spec exists specifically so that implementations may break up misaligned accesses. When they do so, it’s

Please see the embedded reply below.

Hello, I’ve few queries regarding PMP spec for misaligned access. As per the pmp section in privileged spec, there are two lines as follows: “The matching PMP entry must match all bytes of an

Happy new year everybody! Is there a gentle introduction to the RISCV privileged architecture? I'm asking because I have an undergraduate who wants to learn about it so he can contribute Sail

The intent, wrt AIA assigning or setting aside interrupt 30 for bus/system errors, is not that that is the one and only way through which such errors would be reported to system software. Some

NMIs are usually, but not always irrecoverable, as you say (i.e. you can recover if you're lucky about timing or about the use case - probing falls into that category), but there is a proposed

Hi Allen, NMI is not generally recoverable (i.e. if the NMI arrives when the hart is in the early parts of a Machine-Mode trap handler before mepc has been saved). In some systems, Bus Errors can be

I would have thought that NMI is where you would want to put bus or system errors. Not sure I like that, unless they're pretty benign errors (e.g. they're correctable, or even correctable and

FWIW the AIA (Advanced Interrupt Architecture) reserves interrupt 30 for "bus or system errors".

Jonathan HI - Thanks. Good that you noted that. I realized I did not include the h-level CSR that go with the vsqoscfg CSR. The idea is to have a virtual RCID/MCID to physical RCID/MCID mapping where

I only skimmed some of the proposal, but one thing I noticed is that there doesn't seem to be much limit over who can set the current RCID and MCID. In particular, with the H-extension it looks like a

Greetings All! So finally collected these thoughts and put them into a document: https://docs.google.com/document/d/1SfvV0oJHiRa89K5IZkzWL-FtXsAGhOPYrMF9B1-1vp8/edit?usp=sharing The document also has

Think "are considered, for permission checking purposes, to be user-level accesses ...". So No and Yes respectively. In particular, if G-stage U=0, then all these accesses that are treated "as though

The Privileged Spec says: Section 5.5.1 "For G-stage address translation, all memory accesses (including those made to access data structures for VS-stage address translation) are considered to be

Continuing this thread with some more thoughts included. regards ved Quality of service enforcement in caches: ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Caches that support the QoS extension allow

Hi all, I'd like to start a discussion on adding an ability to delegate hardware performance monitoring counters to S/HS mode, and further to VS mode. In “Rich OS” server environments, PMU

My preference is a default that has a deterministic result, rather than "implementation defined" because the costs, if any, are tiny and the upsides aren't.