I wrote: Correction: Interrupts are globally enabled for HS level if the current privilege mode has less privilege than HS (U, VS, or VU mode) or if the current privilege mode is HS and the HS-level

Scott Johnson wrote: Your expectation about the roles of sstatus.SIE and vsstatus.SIE is correct, and you're probably also right to say that this isn't explained clearly in the current Privileged

I expect, and have observed in Spike, that `sstatus.SIE` will apply to interrupts delegated to HS-mode, and `vsstatus.SIE` will apply to interrupts delegated to VS-mode. But I cannot find this

Hi All, On a 64-bit implementation RISCV that supports a writable XML field in the MISA CSR and that supports writing 1 to that field (to turn on 32-bit mode), if we apply section 2.4 (CSR width

Hi Sean, The rocket-chip repo with our H-extension (a.k.a. Rocket-H) implementation can be found here: https://github.com/josecm/rocket-chip/tree/hyp Here you can find instructions on how to build and

Thank you for sending out the announcement, and congratulations :-) I was wondering about the Rocket-H RTL. Did some searching, which didn't turn up much. Is that in the rocket-chip repo? If not,

As I mentioned in my 2/25 response: "This manner of supporting delegation involves defining a bunch of bits. Which is not a clean and scalable solution as other bits in the ip/*ie registers come

Thanks Greg for the prompt response. Yes, AIA is of interest to us. This will allow us to replace the home-grown controller we have now. One last question(s). I assume hideleg[13] is supported

The AIA SIG should be started by early-to-mid March. So a first draft of a proposed spec is coming very soon. (Soon enough, it sounds like, for your timeframe?) The SBI call is for initializing a

If you care about virtualization and having an interrupt controller that supports virtualization and the H-extension, the only game in town is AIA (which is one of the motivating factors for it).

What is the bare-minimum that is required in terms of the CSRs to have the SBI calls work for PMIs? I understand that AIA will be defined, but it is not available at this time. mideleg[13]. Yes,

By default hideleg functionality applies to all bits in the ip/*ie registers.So nothing special or extra needs to be specified in this extension. As one can start to see, this manner of supporting

Thanks for the clarification. Should I assume the following as a standard extension to H-extension? hideleg – add a bit13 for delegation of PMI from HS to VS-mode hip, hie, vsip and vsie –

Thanks. That would be great. Let me also send you (tomorrow) the "final" version as submitted to the OACR committee. Let me get back to you on that (probably after I talk with Andrew). Greg

Ah, branch-to-self - I should have thought of that. (slapping myself upside the head). Then it doesn't matter how long the signal takes. And, we wouldn't even need a particularly deterministic

Another way to test that might work is, to disable the interrupt, set the counter to an overflow value, and then enable interrupts. But.... Unfortunately, the use of an overflow bit outside the

H-extension is already considered in this proposal. We have filter bits for VS/VU modes only events. Linux PMU driver will using SBI PMU extension. The SBI PMU extension will be implemented in

Addendum: without some kind of event standardization, even after all of this, we can only test one counter...not great coverage.

I think I have trouble answering questions concisely. From a Definition of Done perspective, you're supposed to have architectural tests that will pass when run on the Sail model and on Spike - more

These are the sorts of questions I'm about to start grappling with. :) Very possibly (tbd). Which doesn't mean that basic aspects of the extension can't be tested; just that the core functionality